FIFO Reclock Jitter Eliminator for 8 Channel DAC

This FIFO reclock PCB can be soldered directly on the multichannel XMOS PCB. The item image includes the detail.

It is based on the well known flip flop synchronize reclock approach, MCK is used to directly reclock the I2S signal. The MCK from the I2S input is used to drive the input flip flop for FIFO reclock, it do not have the problem as the other complex reclock scheme which drop or double dozens of unnecessary samples every second, and it do not use CPLD/FPGA as the other design which actually increase the jitter tenth of time after reclock. This PCB is target for audiophile.

When using this approach, the jitter on the final output I2S signal stream depends on the MCK, as the MCK on our XMOS PCB is connected directly to the ultra low phase noise NDK oscillator. The oscillator is used directly by the flip flop to reclock and achieve to maximum performance.

*Modern delta sigma DAC(AK4497/PCM1794/AD1955...etc) requires MCK as well as three I2S signal(DATA BCK LRCK) input, I2S signal is already reclocked inside the DAC chip actually. This reclock PCB may still increases the sound quality 10-20%

*For ES9038 ES9028 ES9018 or ES9023 PCB do not requires MCK and using async onboard oscillator(i.e. only three I2S signal input). This reclock PCB may increases the sound quality over 30%.

*All of our R2R (PCM1704/AD1862/TDA1540... etc.) DAC PCB already include onboard FIFO reclock , double reclock with this PCB may only increase the sound quality by 5% but it may not work as race condition may happen in some situation.

Compact size: 54*40mm